`timescale 1ps / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:   15:30:59 01/19/2017
// Design Name:   dark_light_correction
// Module Name:   D:/FPGA_Module/Project_XD017/ImgeProcessLib/Dark_light_correct/dark_light_correction_tb.v
// Project Name:  Dark_light_correct
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: dark_light_correction
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module dark_light_correction_tb;

// Inputs
reg Clock;
reg Reset;
reg Frame_rst;
reg Process_en;
reg [ 13: 0 ] Datain_cur;
reg Datain_valid_cur;

reg [ 13: 0 ] Datain_last;
reg Datain_valid_last;
// Outputs
wire [ 13: 0 ] Dataout;
wire Dataout_valid;

integer w_file;
reg[ 16: 0 ] n;
reg[ 2: 0 ] frame_cnt;
reg[ 9: 0 ] col;
reg[ 15: 0 ] mem_buffer1[ 0: 320 * 256 - 1 ];
reg[ 15: 0 ] mem_buffer2[ 0: 320 * 256 - 1 ];
reg[ 19: 0 ] memb[ 0: 320 * 256 - 1 ];
reg data_valid;
reg[ 19: 0 ] cnt;
reg[ 16: 0 ] i;
wire		o_Data_vld;
wire [13:0]	 	o_Data;
reg i_Clk;
always #5000 i_Clk = ~i_Clk;//100mhz-10000ps

always #13889 Clock = ~Clock;

// always #12500 clk_100m = ~clk_100m;

initial begin
	// Initialize Inputs
	Clock = 1;
	i_Clk = 1;
	Frame_rst = 0;
	Reset = 1;
	Process_en = 0;
	Datain_cur = 0;
	Datain_valid_cur = 0;
	Datain_valid_last = 0;
	i = 0;
	cnt = 0;
	n = 0;
	frame_cnt = 0;

	// Wait 100 ns for global reset to finish
	#100 Reset = 0;

	// Add stimulus here

end


parameter CLK_FREQ = 100_000_000;
parameter FRAME_RATE = 50;
parameter CNT_SYNC = CLK_FREQ/FRAME_RATE;// 2 000 000 000;
parameter CNT_SYNC_MID = CNT_SYNC/2;


reg 	o_Field_sync;
reg[31:0] cnt_field_rst;//2000000000*Clock

always @ (posedge i_Clk) begin//40mhz@60fps=16666667ns
	if(Reset)
		cnt_field_rst <= 32'd0;
	else if(cnt_field_rst == CNT_SYNC-1)
		cnt_field_rst <= 32'd0;
	else
		cnt_field_rst <= cnt_field_rst + 32'd1;
end
always @ (posedge i_Clk) begin//100mhz@50fps = 20000000ns
	if(Reset)
		o_Field_sync <= 1'd0;
	// else if(cnt_field_rst == CNT_SYNC_MID-1 || cnt_field_rst == 32'd1)
	else if(cnt_field_rst == 32'd1)
		o_Field_sync <= ~o_Field_sync;
	else
		o_Field_sync <= o_Field_sync;
end

assign field_rst = (cnt_field_rst == 20'd10) ;



/***********************************/

Master_axi_stream_v1_0 inst_Master_axi_stream_v1_0
	   (
		   // Users to add ports here
		   .i_Clk_sys		(Clock),
		   .i_Rst_n		(~Reset),
		   .Data_valid_in		(),
		   .FPA_data_in		(),
		   .Filter_enable		(),
		   .Filter_threshold		(),
		   .Filter_data		(),
		   .m00_axis_aclk(i_Clk),
		   .m00_axis_aresetn(~Reset),
		   .m00_axis_tvalid(),
		   .m00_axis_tdata(),
		   .m00_axis_tstrb(),
		   .m00_axis_tlast(),
		   .m00_axis_tready(1)
	   );
/***********************************/

endmodule

